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document order number: mc34703 rev 4.0, 02/2006 freescale semiconductor technical data * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2006. all rights reserved. 10 a + switch-mode power supply with ldo regulator the 34703 integrated power supply ic is designed to support the powerquicc? family of mcus as well as other mcus and dsps requiring a high current core supply. the 34703 incorporates a high- performance switching regulator for the microprocessor?s core supply, and a low-dropout (ldo) li near regulator control circuit to provide i/o and bus voltage. the switching regulator is an efficient synchronous buck converter with integrated low r ds(on) high side and low side fets. temperature and current sensing is built in and provides protection for the ic as well as the external circuitry. the 34703 incorporates specific advanced protection features for use with high power processors and controllers, including power-up and power-down sequencing of the i/o and core supply voltages in relation to each other. features ? wide input operating voltage range: 2.8 v to 13.5 v ? adjustable output voltages ? continuous core voltage supply currents up to 10 a (with infrequent excursions to 12 a permitted) ? undervoltage lockout ? selectable power sequencing ? programmable watchdog timer ? voltage margining via i 2 c bus ? overcurrent protection ? reset with programmable power-on delay figure 1. mc34703 simpli fied application diagram integrated power supply ic pnb suffix 98asa10705d 33-terminal pqfn 34703 ordering information device temperature range (t a ) package mc34703pnb/r2 -40 to 85c 33 pqfn 34703 2.8 to 13.5 v vddh (i/o) vddl (core) mcu por vin1 ldrv ldo lfb isns reset sw_a pgnd inv clksel gnd boot vout lcmp addr vddi clksyn freq en1 sda scl en2 vbd vbst (sense) vin2 vbst sr sw_b vbst comp rt optional i 2 c bus
analog integrated circuit device data 2 freescale semiconductor 34703 internal block diagram internal block diagram figure 2. 34703 simplifi ed internal block diagram boost control voltage regulator vddi supply bandgap reference linear regulator control with i lim power sequencing voltage margining watchdog timer uvlo buck hs and ls driver buck control logic reset control por timer reset slew rate i2c oscillator ramp generator vin1 vddi vref vbst vbst vddi vddi vbst vref vref vddi powerdown current limit pwr seq. pwr seq. inv lfb sr 0.8 v syscon 1 2 3 5 5 6 6 7 7 vddi ldrv isns ldo lfb lcmp boot vin2 sw pgnd inv vout comp freq clksyn clksel scl sda addr sr reset en2 en1 vbd vbst vin1 vbst vldo vout vddi gnd q3 q2 q1 q4 rt
analog integrated circuit device data freescale semiconductor 3 34703 terminal connections terminal connections figure 3. 34703 terminal connections bottom view table 1. 34703 termina l definitions a functional description of each terminal can be found in the functional terminal description section beginning on page 15 . terminal number terminal name terminal function formal name definition 1 vbst input boost voltage input for internal boost regulator. the internal boost regulator provides 8 v (at up to 45 ma current) to supply the gate drive circuits for the integrated power mosfets and the external n-channel power mosfet of the linear regulator. 2 en2 input enable terminal 2 enable 2 input. the combination of the logic state of the enable 1 and enable 2 inputs determine operation mode and type of power sequencing of the ic. 3 clksel input/output clock selection this terminal sets the clksyn terminal either as an oscillator output or synchronization input terminal. the clk sel terminal is also used for the i 2 c address selection. 1234567891011 12 13 14 15 16 17 18 19 20 21 22 33 32 26 23 24 28 29 30 27 vin2 sw sw pgnd comp inv boot sr nc (heatsink only) vbst sense en1 vbd sda clksyn vddi gnd rt ldrv lfb vout vbst en2 clksel vin1 scl freq addr reset lcmp isns ldo
analog integrated circuit device data 4 freescale semiconductor 34703 terminal connections 4 v in1 input input voltage 1 the input supply terminal for the integr ated circuit. the internal circuits of the ic are supplied through this terminal. 5 scl input serial clock i 2 c bus terminal. serial clock. 6 freq input oscillator frequency the switcher oscillator frequency can be adjusted by connecting an external resistor r f to the freq terminal. the default switching frequency (freq terminal left open or tied to v ddi ) is ~300 khz. 7 addr input address i 2 c address selection. this terminal can be either left open, tied to v ddi , or grounded through a 10 k ? resistor. 8 reset output reset the reset terminal indicates to t he external circuitry when one of the regulators protection features has been activated. note, since it is an open drain output it has to be pulled up to some supply voltage (e.g., the output of the ldo) by an external resistor. 9 lcmp input linear compensation linear regulator compensation terminal. 10 isns input current sense current sense terminal of the ldo to provide overcurrent protection of the linear regulator?s external power mosfet. the voltage drop over the ldo current sense resistor r s is sensed between the isns and the ldo terminals. the ldo current limit can be adjusted by selecting the proper value of the current sense resistor r s . 11 ldo input linear regulator input terminal of the linear regulator power sequence and current limit control circuits. 12 v bd output boost voltage drain drain of the internal boost regulator's switching power mosfet. 13 vbst sense input boost voltage sense note, this terminal must be connected to vbst (terminal 1) and is not intended to provide power to external circuitry. 14 en1 input enable terminal 1 enable 1 input. the combination of the logic state of the enable 1 and enable 2 inputs determine operation mode and type of power sequencing of the ic. 15 sda input/output serial data i 2 c bus terminal. serial data. 16 clksyn input/output clock sync input/ oscillator output oscillator synchronization input termi nal or oscillator output terminal. the clksyn terminal can be configured either as an oscillator output when the clksel terminal is left open or it can be used as a synchronization input when the clksel terminal is grounded. 17 vddi passive vdd filter internal supply voltage capacitor terminal. a ceramic low esr 1.0 f capacitor in parallel with a ceramic 100nf capacitor should be connected from this terminal to ground. the vddi power supply voltage is for internal use only; do not use externally. 18 gnd signal ground analog ground of the ic. 19 rt passive reset timer this terminal allows programming the power-on reset delay by means of an external rc network. 20 ldrv output ldo gate drive ldo gate drive of the external pass n-channel mosfet. 21 lfb input ldo feedback linear regulator feedback terminal. 22 vout output output voltage power sequencing control this terminal must be directly connect ed to the output voltage of the buck converter. this terminal controls the buck regulators output voltage (vout) in accordance with the power sequencing control mode set by en1 and en2. 23 inv input error amp buck controller error amplifier inverting input. table 1. 34703 terminal de finitions (continued) a functional description of each terminal can be found in the functional terminal description section beginning on page 15 . terminal number terminal name terminal function formal name definition
analog integrated circuit device data freescale semiconductor 5 34703 terminal connections 24 comp input switcher compensation buck converter compensation terminal. 25, 31 these terminals are not present in package. 26 nc heatsink no electrical connection, thermal heatsinking only. 27, 28 sw output switch buck regulator switching node. this terminal is connected to the high power inductor. 29 pgnd power power ground buck regulator and p ower s equencing shunt fets p ower g round. 30 vin2 input input voltage 2 buck regulator power input. drain of the high-side power mosfet. 32 boot input bootstrap bootstrap capacitor input. 33 sr passive slew rate buck converter slew rate control terminal. table 1. 34703 terminal de finitions (continued) a functional description of each terminal can be found in the functional terminal description section beginning on page 15 . terminal number terminal name terminal function formal name definition
analog integrated circuit device data 6 freescale semiconductor 34703 maximum ratings maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings supply voltage v in1 , v in2 -0.3 to 14 v switching node sw -1.0 to 14 v buck regulator bootstrap input (boot - sw) boot -0.3 to 8.5 v differential voltage (sr - sw) v sr -0.3 to 8.5 v boost regulator output (1) v bst -0.3 to 8.5 v boost regulator drain v bd -0.3 to 9.5 v reset drain voltage reset -0.3 to 7.0 v enable terminals (en1, en2) v enable -0.3 to 14 v logic terminals (sda, scl, clksyn) v logic -0.3 to 7.0 v analog terminals (inv, v out ) v analog1 -0.3 to 7.0 v analog terminals (ldrv , lfb, ldo, lcmp, isns) v analog2 -0.3 to 8.5 v analog terminals (clksel, addr, rt, freq, v ddi ) v analog3 -0.3 to 3.6 v esd voltage human body model (2) machine model (3) v esd1 v esd2 2000 200 v thermal ratings storage temperature t stg -65 to 150 c power dissipation (t a = 85c) (4) p d 2.0 w lead soldering temperature (5) t solder 245 c maximum operating junction temperature t jmax 125 c package operating temperature range (ambient temperature) t a -40 to 85 c thermal resistance thermal resistance, junction to ambient (6) r ja 38 c/w thermal resistance, junction to base (7) r jb ~1.0 c/w notes 1. maximum recommended filter capacitor: 10 f. (note, vbst terminal is not short-circuit protected.) 2. esd1 testing is performed in accor dance with the human body model (c zap = 100 pf, r zap = 1500 ? ). 3. esd2 testing is performed in acco rdance with the machine model (c zap = 200 pf, r zap = 0 ? ). 4. maximum still-air power dissipation at i ndicated ambient temperature; higher power di ssipations may be possible with addition al heat- sinking and forced-air cooling. 5. lead soldering temperature limit is for 10 seconds maximum durati on. contact freescale sales offi ce for immersion soldering t ime/ temperature limits. 6. thermal resistance measured in accordance with eia/jesd51-2. 7. theoretical thermal resistance from the di e junction to the exposed heat-sinking terminals.
analog integrated circuit device data freescale semiconductor 7 34703 static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions -40c t j 85 c unless otherwise not ed. input voltages 2.8 v v in 13.5 v. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit general (vin1, vin2, vbst, vddi) (9) operating voltage range (v in1 , v in2 ) v in 2.8 ? 13.5 v start-up voltage threshold (boost switching) v st ? 1.6 1.8 v v bst undervoltage lockout (internal use only) v bstuvlo 5.5 6.0 6.5 v input dc supply current (normal operation mode, enabled) (8) i in ? 60 ? ma v in1 terminal input supply current (en1 = en2 = 0) (8) i in1 ? 13 ? ma v in2 terminal input leakage current (en1 = en2 = 0) (8) i in2 ? 100 ? a output voltage (11) v out 10% v in ? 5.0 v output dc current (10) (11) i out 0.1 ? 12 a buck converter (inv, vout) buck converter feedback voltage i vout = 100 ma to 10 a, v in1 = v in2 = 2.8 v to 13.5 v. no r b resistor. includes load regulation error v inv 0.784 0.8 0.816 v buck converter voltage margining step v mvo ? 1.0 ? % buck converter line regulation (12) v in1 = v in2 = 2.8 v to 13.5 v, i vout = 10 a reg lnvo -1.0 ? 1.0 % buck converter load regulation (12) i vout = 100 ma to 10 a reg ldvo -2.0 ? 2.0 % v out input leakage current v out = 5.0 v i voutlk 1.7 4.6 7.5 ma high-side power mosfet q1 r ds(on) (10) i d = 1.0 a, t a = 25c, v bst = 8.0 v r ds(on) ? ? 25 m ? low-side power mosfet q2 r ds(on) (10) i d = 1.0 a, t a = 25c, v bst = 8.0 v r ds(on) ? ? 10 m ? buck converter peak current limit (high level) i hlim 12 15 19 a buck converter valley current limit (low level) i llim 6.0 7.5 9.0 a v out internal pull-down mosfet current limit t a = 25c, v bst = 8.0 v i q3lim 0.75 1.7 2.0 a v out internal pull-down mosfet r ds(on) i d = 1.0 a, t a = 25c, v bst = 8.0 v q3 r ds(on) ? ? 3.0 ? thermal shutdown (12) t sd 150 170 190 c thermal shutdown hysteresis (12) t sdhys ? 15 ? c notes 8. not production tested; typical values for reference only. 9. v ddi is an internal supply voltage. it s hould not be used for any external purpose. 10. design information only; not production tested. 11. minimum output voltage can be adjusted to 0.8 v when v in < 8 v. maximum currents subject to sufficient heat-sinking. 12. guaranteed by design.
analog integrated circuit device data 8 freescale semiconductor 34703 static electrical characteristics buck error amplifier (inv, comp) input impedance (13) r in ? 14 ? m ? output impedance (13) r out ? 1.4 ? k ? dc open loop gain (13) a vol ? 80 ? db gain bandwidth product (13) gbw ? 4.0 ? mhz slew rate (13) sr ? 2.0 ? v/ s output voltage swing ? high level v in1 > 3.3 v, i oea = -400 ma (13) v eaoh ? 2.0 ? v output voltage swing ? low level i oea = 400 ma (13) v eaol ? 0.4 ? v slope compensation ramp (13) v scramp ? 0.6 ? v oscillator (freq) oscillator low-level output voltage (clksyn terminal), clksel open v oscol ? 0.1 0.4 v oscillator high-level output voltage (clksyn terminal), clksel open (14) v oscoh 2.7 ? 3.3 v oscillator input voltage threshold (clksyn terminal), clksel grounded v oscih 1.2 1.6 2.0 v oscillator frequency adjusting reference voltage (freq) (16) v freq 1.15 1.27 1.35 v oscillator frequency adjusting resistor range (16) r freq 5.0 ? 20 k ? boost regulator (vbst, vin) boost regulator output voltage i bst = 20ma, v in1 = v in2 = 2.8 v to 8.0 v v bst 7.5 8.0 8.5 v boost regulator output voltage (15) i bst = 20ma, v in1 = v in2 > 8.0v v bst(vgreg) 7.5 8.0 8.8 v boost regulator start-up voltage v inbsu ? 1.6 1.8 v boost regulator peak current limit (power fet peak current) i pbd 0.75 1.0 1.5 a boost regulator power fet valley current limit (low level) i lbd 550 600 900 ma boost power fet r ds(on) (16) i bst = 500 ma, v in1 = v in2 = 13.5v r ds(on) ? 900 ? m ? boost regulator recommended output capacitor c bst ? 10 ? f boost regulator recommended output capacitor maximum esr esr cbst ? ? 100 m ? notes 13. design information only. it is not production tested. 14. all internal high level voltages are reference to the vddi voltage. 15. when the input is above 8 v an integrated linear regulator will provide v bst ; under this configuration the external inductor must be removed and the vbd terminal left open (floating) . 16. guaranteed by design. table 3. static el ectrical characteristics (continued) characteristics noted under conditions -40c t j 85 c unless otherwise noted . input voltages 2.8 v v in 13.5 v. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 34703 static electrical characteristics linear regulator (ldo, isns, ldrv, lfb) (17) ldo output voltage range (17) v in1 = v in2 = 2.8 v to 13.5 v, i ldo = 100 ma to 2000 ma v ldo 0.8 ? 4.5 v ldo feedback voltage, lfb terminal connected to ldo terminal v in1 = v in2 = 2.8 v to 13.5 v, i ldo = 100 ma to 2000 ma. includes load regulation error v ldo 0.784 0.8 0.816 v ldo voltage margining step size v mldo ? 1.0 ? % ldo line regulation v in1 = v in2 = 2.8 v to 13.5 v, i ldo = 1000 ma reg lnvldo -1.0 ? 1.0 % ldo load regulation i ldo = 100 ma to 2000 ma reg ldvldo -1.0 ? 1.0 % ldo ripple rejection, dropout voltage v do = 1.0 v, v ripple = +1.0 v p-p (18) sinusoidal, f = 300 khz, i ldo = 500 ma v ldorr ? 26 ? db ldo maximum dropout voltage (v in - v ldo ) (18) v ldo = 2.5 v, i ldo = 2000 ma v do ? 50 ? mv ldo current sense comparator threshold voltage (v cs - v ldo ) v csth 35 45 65 mv ldo terminal input current i ldo 1.0 2.0 4.0 ma ldo feedback input current (lfb terminal) i lfb -1.0 0.04 1.0 a ldo drive output current (ldrv terminal) i ldrv 2.0 4.0 5.0 ma ldo drive current limit (ldrv terminal) (18) i drlim ? 3.6 ? ma isns terminal input leakage current v isns = 5.0 v i snslk 50 125.0 200 a ldo error amplifier input impedance (lfb terminal) (18) r in ? 10 ? ? ldo error amplifier output impedance (lcmp terminal) (18) r out ? 60 ? ? ldo internal pull-down mosfet current limit t a = 25c, v bst = 8.0 v (ldo terminal) i q4lim 0.75 1.7 2.0 a ldo internal pull-down mosfet r ds(on) i d = 1.0 a, t a = 25c, v bst = 8.0 v q4 r ds(on) ? ? 3.2 ? ldo recommended output capacitance c ldo ? 10 ? f ldo recommended output capacitor esr esr cldo ? 100 ? m ? thermal shutdown (ldo pull-down fet q4) (19) t sd 150 170 190 c thermal shutdown hysteresis (19) t sdhys ? 15 ? c soft start duration (power sequencing disabled, en1 = 1, en2 = 1) (18) t ss ? 800 ? s notes 17. the ldo output range is given for the mosfet as depicted on figure 33 . should the customer select another mosfet, it is the customer?s responsibility to properly select the mosfet given the expected power diss ipation, voltage drop across it and any ot her constraint that could impact the mo sfet reliability and range of work. 18. not production tested fo r typical values specified. 19. guaranteed by design. table 3. static el ectrical characteristics (continued) characteristics noted under conditions -40c t j 85 c unless otherwise noted . input voltages 2.8 v v in 13.5 v. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 34703 static electrical characteristics control and supervisory circuits (en1, en2, reset , clksel, addr, rt) enable (en1, en2) input voltage threshold v then 1.2 1.6 2.0 v enable (en1, en2) input voltage threshold hysteresis (21) v ihys ? 0.1 ? v enable (en1, en2) pull-down resistance r pu 30 60 90 k ? reset low-level output voltage, i ol = 5.0 ma v ol ? 0.1 0.4 v reset leakage current, off state, pulled up to 5.0 v i lkg rst ? ? 10 a reset undervoltage threshold on v out ( ? v out /v out) (20) v outi th -12 -7.5 -4.0 % reset overvoltage threshold on v out ( ? v out /v out) (20) v outi th 4.0 7.5 12 % reset undervoltage threshold on v ldo ( ? v ldo /v ldo) (20) v ldoi th -12 -7.5 -4.0 % reset overvoltage threshold on v ldo ( ? v ldo /v ldo) (20) v ldoi th 4.0 7.5 12 % rt voltage threshold v thrt 0.8 1.2 1.5 v rt current source i srt 17 25 34 ma rt saturation voltage, reset timer current = 300 a v satrt ? 45 100 mv maximum value of the rt capacitor c t ? ? 33 f clksel threshold voltage v thclks 1.2 1.6 2.0 v clksel pull-up resistance r puclks 60 120 240 k ? addr threshold voltage v thaddr 1.2 1.6 2.0 v addr pull-up resistance r puaddr 60 120 240 k ? i 2 c bus (sda, scl) input threshold voltage v ith 1.3 ? 1.7 v input voltage threshold hysteresis (21) v ihys ? 0.2 ? v sda, scl input current, input voltage = 0.4 v to 5.5 v i i ? ? 10 a sda low-level output voltage, 3.0 ma sink current v ol ? ? 0.4 v sda, scl capacitance c i ? ? 10 pf notes 20. this parameter does not include the tole rance of the external resistor divider. 21. not production tested fo r typical values specified. table 3. static el ectrical characteristics (continued) characteristics noted under conditions -40c t j 85 c unless otherwise noted . input voltages 2.8 v v in 13.5 v. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 34703 dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions -40c t j 125 c unless otherwise noted. input voltages v in1 = v in2 = 3.3 v using the typical application circuit (see figure 27 ) unless otherwise noted. characteristic symbol min typ max unit buck converter (sw, sr) duty cycle range (normal operation) (22) d 10 ? 90 % switching node sw rise time (22) i load = 10 a, sr = open, v in1 = v in2 = 3.3 v t ropen ? 10 ? ns switching node sw fall time (22) i load = 10 a, sr = open, v in1 = v in2 = 3.3 v t fopen ? 10 ? ns switching node sw rise time (22) i load = 10 a, sr = sw, v in1 = v in2 = 3.3 v t rsw ? 14 ? ns switching node sw fall time (22) i load = 10 a, sr = sw, v in1 = v in2 = 3.3 v t fsw ? 14 ? ns switching node sw rise time (22) i load = 10 a, sr = boot,v in1 = v in2 = 3.3 v t rboot ? 6.0 ? ns switching node sw fall time (22) i load = 10 a, sr = boot, v in1 = v in2 = 3.3 v t fboot ? 6.0 ? ns maximum deadtime (22) t d ? 150 ? ns buck control loop propagation delay (22) v inv < 0.8 v to v sw > 90% of high level or v inv > 0.8 v to v sw < 10% of low level t pd ? 50 ? ns soft start duration (power sequencing disabled, en1 = 1, en2 = 1) (22) t ss 800 s fault condition timeout (22) t fault ? 10 ? ms retry timer cycle (22) t ret ? 100 ? ms oscillator (freq) oscillator default frequency (switc hing frequency), freq terminal open f osc 250 300 350 khz oscillator frequency range f osc 200 400 khz oscillator output signal duty cycle (square wave, 180 out-of-phase with the internal suitable oscillator) (23) d osc ? 50 ? % synchronization pulse minimum duration (22) t sync 300 ? ? ns boost regulator (vbst, vbst (sense), vbd) boost regulator fet maximum on time (23) t on ? 24 ? s boost regulator control loop propagation delay (22) t bstpd ? 50 ? ns boost switching node v bd rise time (22) i bst = 45 ma t br ? 35 ? ns boost switching node v bd fall time (22) i bst = 45 ma t bf ? 5.0 ? ns notes 22. design information only. not production tested. 23. not production tested fo r typical values specified.
analog integrated circuit device data 12 freescale semiconductor 34703 dynamic electrical characteristics linear regulator (ldo) output current slew rate (24) i sr ? 2.5 ? a/ s fault condition timeout (24) t fault ? 10 ? ms retry timer cycle (24) t ret ? 100 ? ms terminal, i 2 c bus (sda, scl) scl clock frequency (25) f scl ? ? 100 khz bus free time between a stop and a start condition (25) t buf 4.7 ? ? s hold time (repeated) start condition (after this period, the first clock pulse is generated.) (25) t hdsta 4.0 ? ? s low period of the scl clock (25) t low 4.7 ? ? s high period of the scl clock (25) t high 4.0 ? ? s sda fall time from v ih_max to v il_min , bus capacitance 10 pf to 400 pf, 3.0 ma sink current (25) t f ? ? 250 ns setup time for a repeated start condition (25) t susta 4.7 ? ? s data hold time for i 2 c bus devices (25) , (26) t hddat 0.0 ? ? s data setup time (25) t sudat 250 ? ? ns setup time for stop condition (25) t susto 4.0 ? ? s capacitive load for each bus line (25) c b ? ? 400 pf notes 24. not production tested fo r typical values specified. 25. design information only. not production tested. 26. the device provides an internal hold time of at least 300 ns for the sda signal (refer to the v ih_min of the scl signal) to bridge the undefined region of the falling edge of scl. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions -40c t j 125 c unless otherwise noted. input voltages v in1 = v in2 = 3.3 v using the typical application circuit (see figure 27 ) unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 13 34703 timing diagrams timing diagrams figure 4. definition of time on the i 2 c bus t hdsta t hddat t sudat t susta t susto t hdsta sr
analog integrated circuit device data 14 freescale semiconductor 34703 electrical performance curves electrical performance curves figure 5. f osc vs ambient temperature figure 6. efficiency vs load current figure 7. buck converter voltage regulation vs load current figure 8. buck converter voltage regulation vs ambient temperature figure 9. quiescent current vs input voltage figure 10. r f vs frequency (r f is r1 in the application schematic on page 34 ) 320 325 330 335 340 345 350 355 360 365 370 -50 0 50 100 c degree fosc (khz ) f osc t a 80 82 84 86 88 90 92 94 024681012 load current (a) efficiency (%) vin=7v, vo=5v vin=7.0v, vout =5.0v -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 024681012 load current (a) voltage regulation (%) -1.00 -0.80 -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 -60 -10 40 90 c degree output voltage regulation (%) t a 0 20 40 60 80 100 0 5 10 15 input voltage (v) quiescent current (ma) vo=3.3v vout =3.3v 250 300 350 400 8 9 10 11 12 13 rf v alu e ( k 0 ) fosc (khz) ? r f
analog integrated circuit device data freescale semiconductor 15 34703 functional description introduction functional description introduction the 34703 power supply integrated circuit is an efficient means to supply the powerqui cc and other families of freescale microprocessors. it incorporates a high- performance synchronous buck regulator, supplying the microprocessor?s core, and a low dropout (ldo) linear regulator providing the microprocessor i/o and bus voltages. this device incorporates many advanced features including up/down power sequencing, undervoltage lock-out, current shut-down limit, and te mperature shut-down limit, to ensure proper operation and protection of the cpu and power system. the device can be configured to support different voltages and modes of operation, permitting the functions to be tailored to the specific application. functional terminal description boost voltage terminal (vbst) internal boost regulator output voltage. the internal boost regulator provides a 45 ma output current to supply the drive circuits for the integrated power mosfets and the external n-channel power mosfet of the linear regulator. the voltage at the vbst terminal is 8.0 v nominal. enable 1 and 2 terminals (en1 and en2) these two terminals permit positive logic control of the enable function and selection of the power sequencing mode concurrently. table 5 depicts the en1 and en2 function and power sequencing mode selection. both en1 and en2 terminals have internal pulldown resistors and both can withstand a short circuit to the supply voltage, 13.5 v. clock selection terminal (clksel) this terminal sets the clksyn terminal as either an oscillator output or a synchronization input terminal. the clksel terminal is also used for the i 2 c address selection. input voltage 1 terminal (vin1) the input supply terminal for the integrated circuit. the internal circuits of the ic are supplied through this terminal. serial clock terminal (scl) i 2 c bus terminal. serial clock. oscillator frequency terminal (freq) this switcher frequency selection terminal can be adjusted by connecting external resistor rf to the freq terminal. the default switching frequency (freq terminal left open or tied to vddi) is ~300 khz. address terminal (addr) the addr terminal is used to set the address of the device when used in an i 2 c communication. this terminal can either be tied to vddi or grounded through a 10 k ? resistor. refer to i 2 c bus operation on page 25 for more information on this terminal. reset output terminal ( reset ) the reset control circuit m onitors both the switching regulator and the ldo feedback voltages. it is an open drain output and has to be pulled up to the logic supply voltage (e.g., the output of the ldo) by an external resistor. the reset control circuit supervises both output voltages?the linear regulator output v ldo and the switching regulator output v out . when either of these two regulators is out of regulation (high or low), the rst terminal is pulled low. there is a 20 s internal delay filter preventing erroneous resets. during power-up sequencing, rst is held low until the reset timer times out. linear compensation terminal (lcmp) linear regulator compensation terminal. current sense terminal (isns) current sense terminal of the ldo. overcurrent protection of the linear regulator external power mosfet. the voltage drop over the ldo current sense resistor rs is sensed between the isns and ldo terminals. the ldo current limit can be adjusted by selecting the proper value of the current sensing resistor rs. table 5. operating mode selection en1 en2 operating mode 0 0 regulators disabled 0 1 standard power sequencing 1 0 inverted power sequencing 1 1 no power sequencing, regulators enabled
analog integrated circuit device data 16 freescale semiconductor 34703 functional description functional terminal description linear regulator terminal (ldo) input terminal of the linear regulator power sequence control circuit. boost drain terminal (vbd) drain of the internal boost regulator power mosfet. vbst (sense) sense terminal of the intern al boost regulator output voltage. serial data terminal (sda) i 2 c bus terminal. serial data. clock synchronization terminal (clksyn) oscillator output/synchronization input terminal. vdd filter terminal (vddi) internal logic supply voltage terminal: a low-esr 1.0 f 6.0 v capacitor must be connected between this terminal and signal ground. reset timer terminal (rt) the reset timer power-up delay (rt) terminal is used to set the delay between the time when the ldo and switcher outputs are active and stable and the rst output is released. an external resistor and capacitor are used to program the timer. the power-up delay can be obtained by using the following formula: t d ~ 10 ms + r t c t where r t is the reset timer programming resistor and c t is the reset timer programming capacitor, both connected in parallel from rt to ground. linear drive terminal (ldrv) ldo gate drive of the external pass n-channel mosfet. linear feedback terminal (lfb) linear regulator feedback terminal. output voltage terminal (vout) output voltage of the buck conv erter. input terminal of the switching regulator power sequence control circuit. error amp inverting input terminal (inv) buck controller error amplifier inverting input. buck switcher compensation (comp) output voltage of the buck converter error amplifier. compensation terminal. switch terminals (sw) buck regulator switching node. this terminal is connected to the inductor. power ground terminals (pgnd) buck regulator power ground. input voltage 2 terminals (vin2) buck regulator power input. drain of the high-side power mosfet. bootstrap terminal (boot) bootstrap capa citor input. switcher slew rate control (sr) buck slew rate control terminal. for faster slew rates, connect the terminal to the boot terminal (boot). for medium speeds, the terminal should be left open. for slowest options, connect the terminal to the switch terminal (sw).
analog integrated circuit device data freescale semiconductor 17 34703 functional description functional internal block description functional internal block description introduction the paragraphs below describe t he functional sub-circuits of the 34703 integrated power supply ic. figure 11. 34703 functional internal block diagram boost regulator a boost regulator provides a high voltage necessary to properly drive the buck regulator power mosfets, especially during the low input voltage condition. the ldo regulator external n-channel mosfet gate is also powered from the boost regulator. in order to properly enhance the high-side mosfets when only a +3.3 v supply rail powers the integrated circuit, the boost regulator provides an output voltage of 8.0 v nominal value. the 34703 boost regulator uses a simple hysteretic current control technique, wh ich allows fast power-up and does not require any compensation. when the boost regulator main power switch (low side) is turned on, the current in the inductor starts to ramp up. after the inductor current reaches the upper curr ent limit (nominally set at 1.0 a), the low-side switch is turned off and the current charges the output capacitor th rough the internal rectifier. when the inductor current falls below the valley current limit value (nominally 600 ma), the low-side switch is turned on again, starting the next switching cycle. after the boost regulator output capacitor reache s its regulation limit, the low- side switch is turned off until the output voltage falls below the regulation limit again. note: should the input voltage be higher than 8.0 v, an internal linear regulator provides the required boost voltage. in this configuration t he external boost inductor must be removed and the vbd terminal left floating !
analog integrated circuit device data 18 freescale semiconductor 34703 functional description functional internal block description figure 12. boost regulator startup (not to scale) buck regulator the buck regulator is a high-frequency (300 khz default, adjustable in the range from 200 khz to 400 khz), synchronous buck converter driving integrated high-side and low-side n-channel power mosfets. the buck regulator output voltage is adjustable by me ans of an external resistor divider to provide the required output voltage. its high current ouput is well suited for direct ly powering the core of the microprocessor. a typical bootstrap technique is used to provide the voltage necessary to properly enhance the high-side mosfet gate. however, when the regulator is supplied from a low-input voltage (e.g., a +3.3 v supply rail), the bootstrap capacitor is charged from the internal boost regulator output v bst through an external diode. this arrangement allows the 34703 to operate efficiently even from a very low input voltage source. figure 13. switching regulator current limit (not to scale) in order to avoid destruction of the supplied circuits, a current limit with retry capability was implemented in the buck regulator. when an overcu rrent condition occurs and the switch current reaches the peak current limit value, the main (high-side) switch is turned o ff until the inductor current decays to the valley value, wh ich is one-half of the peak current limit. if an overcu rrent condition exists for 10 ms, the buck regulator control circuit shuts the switcher off and the switcher retry timer starts to time out. when the timer expires after 100 ms, the switcher engages the start-up sequence and runs for 10 ms, repeatedly checking for the overcurrent condition. during the current limited operation (e.g., in case of short circuit on the buck regulator output), the buck regulator operation is not sync hronized to the oscillator frequency. the buck regulator output vo ltage can be adjusted from 0.8 v to 5.0 v. power-up, power-down, and fault management are coordinated with the linear regulator. figure 14. buck converter overcurrent protection 6.0 v 7.7 5 v i pk =1atyp. 0.6 a typ . 0.2 a t yp. 0.1 a typ . booster output voltage 0v bo ost er ind u ct or current i pk 0.5 i pk t fa u l t =10ms cu rrent limit i pk 0.5 i pk t fault =10ms 0a t ret =100ms fault timer retry timer
analog integrated circuit device data freescale semiconductor 19 34703 functional description functional internal block description figure 15. ldo converter overcurrent protection switching oscillator a 300 khz (default) oscillator se ts the switching frequency of the buck regulator. the frequency of the oscillator can be adjusted between 200 khz and 400 khz by an optional external resistor r f connected from the freq terminal of the integrated circuit to ground. see figure 10 for frequency resistor selection. the clksyn terminal can be co nfigured eith er as an oscillator output when the clksel terminal is left open or it can be used as a synchroniza tion input when the clksel terminal is grounded. the oscill ator output signal is a square wave logic signal with 50 percent duty cycle, 180 degrees out-of-phase with the internal clock signal. this allows opposite phase synchronization of two 3370x devices. when the clksyn terminal is used as synchronization input (clksel terminal grounded), the external resistor r f chosen from the chart in figure 10 should be used to synchronize the internal ramp generator to the external clock. operation is only recommended between 200 khz and 400 khz. the supplied synchronization signal does not need to be 50 percent duty cycle. minimum pulse width is 300 ns. low dropout linear regulator (ldo) the adjustable low dropout linear regulator (ldo) is capable of supplying up to a 2.0 a output current. it has a current limit feature with retry capability. current limiting is implemented via a sense resistor that feeds back a small voltage to the isns terminal. when the sense resistor is used, the contro l circuit limits the current for 10 ms when the voltage measured across the current sense resistor reaches a 45 mv threshold. if the overcurrent condition still exists after the 10ms time period, the linear regulator is turned off. at the same time the overcurrent condition is detected, the retr y timer starts to count down. when the timer expires after 100 ms, the ldo tries to power up again for 10 ms, repeatedly checking for the overcurrent condition. the current limit of the ldo is determined by the following formula: i lim = 45 mv / r s where r s is the ldo current sense resistor, connected between the isns terminal and the ldo terminal output (see figure 27 ). the output voltage of the ldo can be adjusted by means of an external resistor divi der connected to the feedback control terminal lfb. the linear regulator output voltage can be adjusted in the range of 0.8 v to 5.0 v, but the ldo output voltage is always lower than the input voltage to the regulator. power-up, power-down, and fault management are coordinated with the switching regulator. thermal shutdown in order to increase the over all safety of the system designed with the 34703, an internal thermal shutdown function has been incorporated into the switching regulator circuit. the 34703 senses the temperature of the buck regulator main switching fet (high-side fet q1; see figure 2 ), the low-side (synchronous fet q2), and control circuit. if the temperature of any of the monitored components exceeds the limit of safe operation (thermal shutdown), the switching regulator will be shut down. after the temperature falls below the value given by the thermal shutdown hysteresis window, the switcher will retry to operate again. the v out /ldo pull-down fets q3/q4 have an independent thermal shutdown control. when the q3/q4 temperature exceeds the therma l shutdown limit, q3/q4 will be turned off without affect ing the switcher operation. the maximum junction temperature is 125 c and thermal shutdown is 170 c. it is not recommended to operate this ic beyond these thresholds. watchdog timer a watchdog function is available via i 2 c bus communication. it is possible to select either window watchdog or time-out watchdog operation, as illustrated in figure 16 . watchdog time-out starts w hen the watchdog function is activated via i 2 c bus sending a watchdog programming command byte, thus determining watchdog operation (window or time-out) and period duration (refer to table 6 ). if the watchdog is cleared by receiving a new watchdog programming command through the i 2 c bus, the watchdog timer is reset and the new time-out period begins. if the watchdog time expires, the reset will become active (low) for a time determined by the rc components of the rt timer plus 10 ms. after a watchdog time-o ut, the function is no longer active. when the window watchdog function is selected, the timer cannot be cleared during the closed window time, which is 50% of the tota l watchdog period. when the watchdog is cleared, the timer is reset and starts a new time-
analog integrated circuit device data 20 freescale semiconductor 34703 functional description functional internal block description out period. if the watchdog is not cleared during the open window time, the reset will become active (low) for a time determined by the rc components of the rt timer plus 10 ms. figure 16. watchdog operation table 6. watchdog programming command byte (as a 2nd command byte) 50% of watchdog period watchdog period timing selected via i 2 c bus ? see table 1 watchdog closed no watchdog clear allowed window open for watchdog clear window open for watchdog clear watchdog period timing selected via i 2 c bus ? see table 1 window watchdog time-out watchdog address value action 0 1 1 0 0 0 0 0 1st command 0 1 1 0 0 0 0 0 wd off (27) 0 1 1 0 1 0 0 0 wd 1280 ms winoff 0 1 1 0 1 0 0 1 wd 320 ms winoff 0 1 1 0 1 0 1 0 wd 80 ms winoff 0 1 1 0 1 0 1 1 wd 20 ms winoff 0 1 1 0 1 1 0 0 wd 1280 ms winon 0 1 1 0 1 1 0 1 wd 320 ms winon 0 1 1 0 1 1 1 0 wd 80 ms winon 0 1 1 0 1 1 1 1 wd 20 ms winon notes 27. the watchdog feature will be turned on automatically after receiving any other valid command byte changing watchdog time.
analog integrated circuit device data freescale semiconductor 21 34703 functional device operation operational modes functional device operation operational modes soft start a switching regulator and ldo soft start feature is incorporated in the 34703. the soft start is active each time the ic is enabled, v in is reapplied, or after a fault retry. other transient events do not activate the soft start. voltage margining the 34703 includes a voltage margining feature accessed through the i 2 c bus. voltage margining allows for independent adjustment of the switcher v out voltage and the linear output v ldo . each can be adjusted up and down in 1% steps to a range of 7%. this feature allows for worst case system validation; i.e., determining the design margin. margining details are describ ed in the section entitled i 2 c bus operation , beginning on page 25 of this datasheet. power sequencing modes the power sequencing of the two outputs of this power supply ic is in compliance with the freescale power quicc and other 32-bit microproce ssor requirements. when the input voltage is applied, the switcher and linear regulator outputs follow the supply rail voltage during powering up and down in the limits given by the microcontroller power sequencing specification, illustrated in figures 17 through 19 . there are two possible power sequencing modes, standard and inverted, as explained below. the third mode of operation is power sequencing disabled. standard power sequencing when the power supply ic operates in the standard power sequencing mode, the switcher output provides the core voltage for the microprocessor. this situation and operating conditions are illustrated in figure 17 and figure 18 . table 5 , page 15 , shows the power sequencing mode selection. inverted power sequencing when the power supply ic is operating in the inverted power sequencing mode, the linear regulator (ldo) output provides the core voltage for the microprocessor, as illustrated in figure 19 . table 5 , page 15 , shows the power sequencing mode selection. figure 17. standard power up / down sequence in +3.3 v supply system ? v = 2.5 v max. lead ? v = 0.4 v max. lag ? v = 2.5 v max. lead slope 1.0 v/ms (typ.) v start-up 3.3 v input supply (i/o voltage) 1.8 v core voltage 34703 3.3 vinput vddh (i/o) vddl ( c ore) mcu por vin1 ldrv ldo lfb isns reset sw_a pgnd inv c lksel gnd boot vout l c mp addr vddi c lksyn freq en1 sda s c l en2 vbd vbst (sense) vin2 vbst sr sw_b vbst c omp rt 1.5 v other c ircuits 2.5 v optional
analog integrated circuit device data 22 freescale semiconductor 34703 functional device operation operational modes figure 18. standard power up / down sequence in +5.0 v supply system figure 19. inverted power up / down sequence in +5.0 v supply system power sequencing requirements 1. i/o supply voltage not to exceed core voltage by more than 2.5 v. 2. core supply voltage not to exceed i/o voltage by more than 0.4 v. methods of control the 34703 has several methods of monitoring and controlling the regulator output voltages, as described in the paragraphs below. power sequencing control is also achieved through the intrinsic operation of the regulators. the en1 and en2 terminals can be used to disable the power sequencing (refer to table 5 , page 15 ). intrinsic operation for both the ldo and switcher, whenever the output voltage is below the regulation point, the ldo external pass fet will be on or the buck high-side fet will be on at a duty cycle controlled by th e switcher. because these devices are fets, current can flow in either direction, balancing the voltages via the common supply terminal. the ability to maintain the fets on will depend on the available gate voltage, and thus the size of the boost regulator storage capacitor. standard power se quencing control comparators monitor voltage differences between the ldo (ldo terminal) and the switcher (v out terminal) outputs as follows: 1. ldo > v out + 2.3 v, turn off ldo. the ldo can be forced off. this occurs whenever the ldo output voltage exceeds the switcher output voltage by more than 2.3 v. 2. ldo > v out + 2.4 v, shunt ldo to ground. if turning off the ldo is insufficient and the ldo output voltage exceeds the switch er output voltage by more than 2.4 v, a 1.0 ? shunt fet is turned on that discharges the ldo load capacitor to ground. the shunt fet is used for switcher output shorts to ground and for power down in case of v in1 v in2 with the switcher output falling faster than the ldo. 3. ldo < v out + 2.2 v, cancel (1) and (2) above, re- enable ldo. normal operation resumes when the ldo output voltage is less than 2.2 v above the switcher output voltage. 4. ldo < v out - 0.1 v, turn off switcher. the switcher can be forced off. this occurs whenever the ldo is less than v out - 0.1 v. 5. ldo < v out - 0.3 v, turn on sync (ls) fet and 1.0 ? v out sink fet. the buck high-side fet is forced off and the sync fet is forced on. this occurs when the ? v = 2.5 v max. lead ? v = 0.4 v max. lag ? v = 0.4 v max. lag v start-up 3.3 v i/o voltage (v ldo ) 1.8 v core voltage (v out ) 5.0 v input supply ? v = 2.5 v max. lead 34703 5.0 vinput vddh (i/o) vddl ( c ore) mcu por vin1 ldrv ldo lfb isns reset sw_a pgnd inv c lksel gnd boot vout l c mp addr vddi c lksyn freq en1 sda s c l en2 vbd vbst (sense) vin2 vbst sr sw_b vbst c omp rt 3.3 v 1.5 v 5.0 v optional ? v = 2.5 v max. lead ? v = 0.4 v max. lag ? v = 0.4 v max. lag v start-up 3.3 v i/o voltage (v out ) 1.8 v core voltage (v ldo ) 5.0 v input supply ? v = 2.5 v max. lead 34703 5.0 vinput vddl ( c ore) vddh (i/o) mcu por vin1 ldrv ldo lfb isns reset sw_a pgnd inv c lksel gnd boot vout l c mp addr vddi c lksyn freq en1 sda s c l en2 vbd vbst (sense) vin2 vbst sr sw_b vbst c omp rt 3.3 v 1.5 v 5.0 v optional
analog integrated circuit device data freescale semiconductor 23 34703 functional device operation operational modes switcher output voltage ex ceeds the ldo output by more than 300 mv. 6. ldo > v out , reset (4) and (5) above. normal operation resumes when ldo > v out . inverted power sequencing control comparators monitor voltage differences between the switcher (v out terminal) and ldo (ldo terminal) outputs as follows: 1. v out > ldo + 2.2 v, turn off v out . the switcher v out can be forced off. this occurs whenever the v out output voltage exceeds t he ldo output voltage by more than 2.3 v. 2. v out > ldo + 2.4 v, shunt v out to ground. if turning off the switcher v out is insufficient and the v out output voltage exceeds the ldo output voltage by more than 2.4 v, a 1.0 ? shunt fet is turned on that discharges the v out load capacitor to ground. the shunt fet is used for ldo output shorts to ground and for power-down in case of v in1 v in2 with ldo output falling faster than the v out . 3. v out < ldo + 2.2 v, cancel (1) and (2) above, re- enable v out . normal operation resumes when the v out output voltage is less than 2.2 v above the ldo output voltage. 4. v out < ldo - 0.2 v, turn off ldo. the ldo can be forced off. this occurs whenever the v out is less than v ldo - 0.2 v. 5. v out < ldo - 0.3 v, turn on the 1.0 ? ldo sink fet. this occurs when the ldo output voltage exceeds the v out output by more than 300 mv. 6. v out > ldo, reset (4) and (5) above. normal operation resumes when v out > ldo. standard operating mode single 3.3 v supply, v in = v in1 = v in2 = 3.3 v the 3.3 v supplies the microprocessor i/o voltage, the switcher supplies core voltage (e.g., 1.8 v nominal), and the ldo operates independently (see figure 17 , page 21 ). power sequencing depends only on the normal switcher intrinsic operation to control the buck high-side fet. power up when v in is rising, initially v out will be below the regulation point and the buck high-side fet will be on. in order not to exceed the 2.5 v differential requirement between the i/o (v in ) and the core (v out ), the switcher must start up at 2.5 v or less and be able to maintain the 2.5 v or less differential. the ma ximum slew rate for v in is 1.0 v/ms. power down when v in is falling, v out will be below the regulation point; therefore the buck high-side fet will be on. in the case where v out is falling faster than v in , the buck high-side fet will attempt to maintain v out . in the case where v in is falling faster than v out , the buck high-side fet is also on, and the v out load capacitor will be discharged through the buck high-side fet to v in . thus, provided v in does not fall too fast, the core voltage (v out ) will not exceed the i/o voltage (v in ) by more than a maximum of 0.4 v. shorted load 1. v out shorted to ground. this will cause the i/o voltage to exceed the core voltage by more than 2.5 v. the load is protected by a current limit. 2. v in shorted to ground. until the switcher load capacitance is discharged, the core voltage will exceed the i/o voltage by more than 0.4 v. by the intrinsic operation of the switcher, the load capacitor will be discharged rapidly through the buck high-side fet to v in . 3. v out shorted to supply. no load protection. 34703 protected by a thermal limit. single 5.0 v supply, v in1 = v in2 , or dual supply v in1 v in2 the ldo supplies the microprocessor i/o voltage. the switcher supplies the core (e.g., 1.8 v nominal) (see figure 18 , page 22 ). power up this condition depends upon th e regulator current limit, load current and capacitance, and the relative rise times of the v in1 and v in2 supplies. there are 2 cases: 1. ldo rises faster than v out . the ldo uses control methods (1) and (2) described in the methods of control section, page 22 . 2. v out rises faster than ldo. the switcher uses control methods (4) and (5) described in the methods of control section. power down this condition depends upon the regulator load current and capacitance and the relative fall times of the v in1 and v in2 supplies. there are 2 cases: 1. v out falls faster than ldo. the ldo uses control methods (1) and (2) described in the methods of control section, page 22 . in the case v in1 = v in2 the intrinsic operation will turn on both the buck high-side fet and the ldo external pass fet, and will discharge the ldo load capacitor into the v in supply.
analog integrated circuit device data 24 freescale semiconductor 34703 functional device operation operational modes 2. ldo falls faster than v out . the switcher uses control methods (4) and (5) described in the methods of control section. shorted load 1. v out shorted to ground. the ldo uses method (1) and (2) described in the methods of control section. 2. ldo shorted to ground. the switcher uses control methods (4) and (5) described in the methods of control section, page 22 . 3. v in1 shorted to ground. this is equivalent to the ldo output shorted to ground. 4. v in2 shorted to ground. this is equivalent to the switcher output s horted to ground. 5. v out shorted to supply. no load protection. 34703 protected by current lim it and thermal limit. 6. ldo shorted to supply. no load protection. 34703 protected by current lim it and thermal limit. inverted operating mode single 3.3 v supply, v in = v in1 = v in2 = 3.3 v the 3.3 v supplies the micr oprocessor i/o voltage, the ldo supplies core voltage (e.g., 1.8 v nominal), and the switcher v out operates independently. power sequencing depends only on the normal ldo intrinsic operation to control the pass fet. power up when v in is rising, initially ldo will be below the regulation point and the pass fet will be on. in order not to exceed the 2.5 v differential requirement between the i/o (v in ) and the core (ldo), the ldo must start up at 2.5 v or less and be able to maintain the 2.5 v or less differential. the maximum slew rate for v in is 1.0 v/ms. power down when v in is falling, ldo will be below the regulation point; therefore the pass fet will be on. in the case where ldo is falling faster than v in , the pass fet will attempt to maintain ldo. in the case where v in is falling faster than ldo, the pass fet is also on, and the ldo load capacitor will be discharged through the pass fet to v in . thus, provided v in does not fall too fast, the core voltage (ldo) will not exceed the i/o voltage (v in ) by more than maximum of 0.4 v. shorted load 1. ldo shorted to ground. this will cause the i/o voltage to exceed the core voltage by more than 2.5 v. the load is protected by a current limit. 2. v in shorted to ground. until the ldo load capacitance is discharged, the core voltage will exceed the i/o voltage by more than 0.4 v. by the intrinsic operation of the ldo, the load capacitor will be discharged rapidly through the pass fet to v in . 3. ldo shorted to supply. no load protection. single 5.0 v supply, v in1 = v in2 , or dual supply v in1 v in2 the switcher v out supplies the microprocessor i/o voltage. the ldo supplies the co re (e.g., 1.8 v nominal) (see figure 19 , page 22 ). power up this condition depends upon th e regulator current limit, load current and capacitance, and the relative rise times of the v in1 and v in2 supplies. there are 2 cases: 1. v out rises faster than ldo. the switcher v out uses control methods (1) and (2) described in the methods of control section, page 23 . 2. ldo rises faster than v out . the ldo uses control methods (4) and (5) described in the methods of control section. power down this condition depends upon the regulator load current and capacitance and the relative fall times of the v in1 and v in2 supplies. there are 2 cases: 1. ldo falls faster than v out . the v out uses control methods (1) and (2) described in the methods of control section, page 23 . in the case v in1 = v in2 the intrinsic operation will turn both the buck high-side fet and the ldo external pass fet, and will discharge the v out load capacitor into the v in supply. 2. v out falls faster than ldo. the ldo uses control methods (4) and (5) described in the methods of control section. shorted load 1. ldo shorted to ground. the v out uses methods (1) and (2) described in the methods of control section, page 23 . 2. v out shorted to ground. the ldo uses control methods (4) and (5) described in the methods of control section. 3. v in1 shorted to ground. this is equivalent to the ldo output shorted to ground. 4. v in2 shorted to ground. this is equivalent to the switcher v out output shorted to ground. 5. ldo shorted to supply. no load protection. 6. v out shorted to supply. no load protection. 34703 protected by a thermal limit.
analog integrated circuit device data freescale semiconductor 25 34703 functional device operation logic commands and registers logic commands and registers i 2 c bus operation the 34703 device is compatible with the i 2 c interface standard. sda and scl terminals are the serial data and serial clock terminals of the i 2 c bus. i 2 c command and data formats communication start communication starts with a start condition, followed by the slave device unique address. figure 20 illustrates the data transfer beginning an i 2 c communication for a 7-bit slave address. figure 20. communication using 7-bit address slave address definition the 34703 has the two lsb?s address bits defined by the state of the clksel terminal and the addr terminal. note the state of the clksel te rminal also defines the configuration of the oscillator synchronization clksyn terminal. this feature allows up to four 34703 ics to communicate in the same i 2 c bus, all of them sharing the same high-order address bits. a different combination of bits a1 and a0 is assigned to each individual part to assure its unique address. figure 21 illustrates the flexible addressing feature for a 7-bit address. table 7 provides the definition of the selectable portion of the device address. figure 21. address bit de finition for 7-bit address writing data into the slave device after the address acknowledgm ent by the slave, data can be written into the slave registers. the r/w bit must be set to 0 so data will be written. figure 22 shows the data write sequence. actions perfo rmed by the slave device are grayed. figure 22. data transfer for write operations data definition for the sake of the 34703 acting as a slave device, the master writes a command byte and writes one data byte. the command byte identifies the kind of operation required by the master and has two fields, as illustrated in figure 23 : 1. address field 2. value field the address field is selected from the list in table 8 . figure 23. command byte table 8. address field definitions refer to table 10 , page 26 , which summarizes the value field definitions for the entire set of operation options. table 7. definition of selectable portion of device address clksel terminal addr terminal a1 a0 low low 0 0 low open 0 1 open low 1 0 open open 1 1 s 7-bit address r/w ack 1 0 2 3 4 5 6 11101a1a0 bits fixed address selectable address code operation write 001 voltage margining w 010 not used ? 011 watchdog w s 7-bit address 0ack data ack (w i ) d6 d5 d4 d3 d1 d0 bits address field value field 7 d7 d2 3210 4 5 6
analog integrated circuit device data 26 freescale semiconductor 34703 functional device operation logic commands and registers security in writing commands all writing operations are critical and must not be inadvertently latched after a fa lse command. to improve the security level, a so-called first command is defined to initiate each write communications. a first command has the command byte address field equal to the related operation one, followed by a null value field (all zeros). table 9 summarizes first command definitions. the master sends the first command before the command byte for the intended operation. voltage margining operation after starting the communication in writing mode, the master sends the first comman d followed by the specific command byte to set the required voltage margining for either the ldo or the switcher (see figure 24 ). to achieve a simultaneous set for both ldo and switcher, two specific commands must be issued in sequence after the first command, one for each supply. figure 24. voltage margining programming (one supply only) note x bits are defined in table 10 , page 26 . watchdog programming operation for watchdog operation control, the master periodically sends a watchdog first command followed by a command byte selecting, or confirming, the watchdog period according to the options listed in table 10 , page 26 . also see figure 25 . the internal watchdog timer will be cleared each time a watchdog command is written into the device, provided it arrives during the window open time. the command 01100000 sent twice will shut the time off, and the watchdog function will be disabled. any other valid watchdog command turns on the timer again. figure 25. watchdog timer programming note x bits are defined in table 10 , page 26 . table 10. command byte definitions table 9. first command definitions first command operation 001 00000 voltage margining 011 00000 watchdog programming 00 00000 10 01 x x x x x first byte for voltage margining command byte ack 01 00000 11 01 x x x x x first byte for watchdog programming command byte ack operation address value action voltage margining (as a 2nd command byte) 0 0 1 0 0 0 0 0 1st command 0 0 1 x 0 0 0 0 output normal 0 0 1 x 0 0 0 1 + 1% 0 0 1 x 0 0 1 0 + 2% 0 0 1 x 0 0 1 1 + 3% 0 0 1 x 0 1 0 0 + 4% ldo output: x = 0 0 0 1 x 0 1 0 1 + 5% switcher output x = 1 0 0 1 x 0 1 1 0 + 6% 0 0 1 x 0 1 1 1 + 7% 0 0 1 x 1 0 0 1 - 1% 0 0 1 x 1 0 1 0 - 2% 0 0 1 x 1 0 1 1 - 3% 0 0 1 x 1 1 0 0 - 4% 0 0 1 x 1 1 0 1 - 5% 0 0 1 x 1 1 1 0 - 6% 0 0 1 x 1 1 1 1 - 7% watchdog programming (as a 2nd command byte) 0 1 1 0 0 0 0 0 1st command 0 1 1 0 0 0 0 0 wd off (28) 0 1 1 0 1 0 0 0 wd 1280 ms winoff 0 1 1 0 1 0 0 1 wd 320 ms winoff 0 1 1 0 1 0 1 0 wd 80 ms winoff 0 1 1 0 1 0 1 1 wd 20 ms winoff 0 1 1 0 1 1 0 0 wd 1280 ms winon 0 1 1 0 1 1 0 1 wd 320 ms winon 0 1 1 0 1 1 1 0 wd 80 ms winon 0 1 1 0 1 1 1 1 wd 20 ms winon notes 28. the watchdog feature will be tu rned on automatically after receiving any other valid command byte changing watchdog time.
analog integrated circuit device data freescale semiconductor 27 34703 functional device operation logic commands and registers communication stop only the master can terminate the data transfer by issuing a stop condition. the slave waits for this condition to resume its initial state waitin g for the next start condition (see figure 26 ). data transfer example the master device controlling the i 2 c bus will always start addressing a 34703 slave ic in writing mode (r/w = 0) in order to be able to write a co mmand byte just after the address acknowledge. i 2 c bus protocol defines this circumstance as a master-transmitter and slave-receiver configuration. eventually this command byte can again define a write operation (e.g., voltage margining, see figure 26 ), and the master will keep the data transfer direction. figure 26 illustrates a communication beginning with the slave address, the first command for voltage margining, and a third byte containing the address field 001 and the value field 00101 corresponding with the ldo fifth setting (ldo output voltage = +5% above its nominal value). if a simultaneous setting for switcher is needed, a fourth byte should be included before the stop condition (p); for instance, 001 10010 to set switcher in its second setting (switcher output voltage = +2 % above its nominal value). figure 26. complete data transfer example start slave address write first command for voltage margining address field value field = ldo 5 th setting stop p ack a6 a4 a0 0010 0 0ack 00 ack 00 1 00 10 1 s a5 a3 a2 a1 0
analog integrated circuit device data 28 freescale semiconductor 34703 typical application logic commands and registers typical application figure 27. 34703 typical application boost regulator when the input voltage to be used is less than 8.0 v, the boost regulator should be used. the boost regulator is made active by adding a small external inductor, and provides an output voltage of 8.0 v nominal value for driving the gates of the buck regulator power mosfets, the linear regulator power mosfet gate, and also for the internal v ddi supply. the boost inductor value should be at least 10 uh for the proper boost operation. note: if the input voltage to be used is greater than 8 v, the boost regulator must not be implemented, and the boost indu ctor, if present, must be removed from the circuit. a 0.1 f capacitor is recommended to be added at terminal vbst for filtering high frequency noise in the system board. buck regulator output voltage setting the buck output voltage is set by an external resistor network (r 9 and r 14 ) and an internal reference voltage. the external resistor network feeds back the dc output voltage, and an error amplifier compares it with an internal reference voltage v ref (see figure 28 ). the buck output voltage can be calculated from the following equation: where v ref designed in mc34703 is 0.8 v typ. boost control voltage regulator vddi supply bandgap reference linear regulator control with i lim power sequencing voltage margining watchdog timer uvlo buck hs and ls driver buck control logic reset control por timer reset slew rate i2c oscillator ramp generator vin1 vddi vref vbst vbst vddi vddi vbst vref vref vddi powerdown current limit pwr seq. pwr seq. inv lfb sr 0.8 v syscon 1 2 3 5 5 6 6 7 7 vddi ldrv isns ldo lfb lcmp boot vin2 sw pgnd inv vout comp freq clksyn clksel scl sda addr sr reset en2 en1 vbd vbst vin1 +3v3 +3v3 +3v3 +3v3 vbd +3v3 vldo = 2v5 @ 2 a vout = 1v2 @ 10 a q3 q2 q1 q4 vbst vldo vout rt vddi gnd v output v vef 1r 9 r 14 ? + () =
analog integrated circuit device data freescale semiconductor 29 34703 typical application logic commands and registers if r 9 is chosen as 5.1 k ? (recommended), r 14 will be calculated as 4.08 k ? for the output voltage of 1.8 v; in a same manner, r 14 is 1.63 k ? for an output voltage of 3.3 v. we recommend using 1% tolerance resistors (r 9 and r 14 ) for the precise output voltage. the following table shows the recommendation values of r 9 and r 14 as referred to different buck output voltages: compensation loop determination the mc34703 has a simple pwm voltage mode control loop to achieve an excellent line and load regulation. the goal for the compensation loop circuit design is to achieve as high as possible unit gain crossover frequency with a gain slope of -1, and enough phase margin ( at least 45) for the closed loop transfer function. the bandwidth should be between 20 -30% of the switch ing frequency. in the power system, there is a double pole crea ted by the output lc filter, and a zero generated by out put capacitor esr (equivalent series resistance). the poles are located: the zero is located: where c o is the capacitance of the output capacitor, l o is the inductance of the output filter inductor. r esr is the total equivalent series resistan ce of output capacitors. based on the typical system conditions, the type 3 compensation scheme has been chosen to use as shown in figure 28 . figure 28. buck regulator compensation circuit table 11. recommendation of r 9 and r 14 value for different output voltage vo r9 (k ? ) r14 (k ? ) 0.8 5.1 ? 1.8 5.1 4.12 2.0 5.1 3.4 3.3 5.1 1.65 5.0 5.23 1.0 f p1 p2 , 1 l o c o 2 ----------------------------- - = f z1 1 2 r esr c 0 -------------------------------------- - = inv + comp + co1 c26 r9 r12 lo vout error amplifier pwm comparator c24 c2 r5 r14 vref ( 0.8 v) saw voltage sw high side low side gate drivers vin vref
analog integrated circuit device data 30 freescale semiconductor 34703 typical application logic commands and registers the location of the three poles and two zeros from the transfer function is shown by the following equations: figure 29 shows the asymptotic bode gain and phase plot for the type 3 compensation scheme. the poles and /or zeroes are adjusted in order to shape the gain profile and make sure the phase has sufficient margin (to meet the system stability criteria). figure 29. bode and phase plot for type compensation scheme output inductor calculation if the output inductor is de signed to guarantee the buck regulator will operate at critic al mode or continuous mode within all load conditions, the following equation will be used to calculate the inductance of the output inductor: where l is the output inductor value in henries, v in is the input voltage in volts, i output is the minimum output current in amps, and f s is the switching frequency in hertz. in this equation, the magnitude of the ripple current is assumed as 2 times minimum load current. for example: input voltage is 5.5 v, minimum output current is 0.2 a, output voltage is 1.8 v, the operating frequency is 300 khz, the inductance of output inductor is calculated as 10 h for an initial value. output capacitor calculating the minimum capacitance of output capacitor could be calculated from the following equation: f sp1 , 0 = f sp2 , c 2 c 24 + 2 r 5 c 2 c 24 ----------------------------------------------- = f sp3 , 1 2 r 12 c 26 ------------------------------------ - = f sz1 , 1 2 r 5 c 24 ---------------------------------- = f sz2 , 1 2 r 9 r 12 + () c 26 ------------------------------------------------------ = fs,z1 fs,z2 fs,p2 fs,p3 fs,p1 90 - 90 0 gain (db) phase (o) frequency (hz) frequency (hz) f s,p 1 f s,z1 f s,z2 f s,p 2 f s,p 3 l v output v in v output ? () 2i output v in f s --------------------------------------------------------------------- - c o min v output 8f s 2 l v pp ? ---------------------------------------------- - 1d ? () =
analog integrated circuit device data freescale semiconductor 31 34703 typical application logic commands and registers where d is minimum switching duty cycle, f s is the operating frequency in hertz, l is output inductance in henries, and ? v pp is output ripple voltage in volts. for example, if the output vo ltage is 1.8v, the minimum duty cycle is 33%, the operat ing frequency is 300 khz, the inductance is 10h and ? v pp is 50 mv, the minimum capacitance of output capacitor will be calculated as 3.3 f, as start value. however, this value is only concerned with the ripple voltage. in the system, one needs to consider load changes from overload to mini mum load and keep the output voltage within spec, so that th e actual output capacitor value varies with the system requirements. the relationship between the ripple voltage and the esr of output capacitor is shown as follows: output curren t limit setting the default setting of the limit is 11 a. when the output current exceeds 11 a, the current limit timer starts to time out while the control circuit limits th e output current. if the over current condition lasts for more than 10 ms, the buck regulator is shut off and tuned on again after 100 ms. this type of operation provides equiva lent protection to the analog ?current fold-back? operation. see figure 30 . figure 30. buck is in the over current condition when the buck output current (channel 3) reaches and exceeds limit, reset terminal (channel 1) is pulled down immediately. channel 4 is buck output voltage (1.8v); channel 2 is ldo output voltage (3.3v). linear regulator output voltage setting the output voltage (v ldo ) of the linear regulator (ldo) can be set by the following equation: where v ref is the linear regulator reference voltage, typically is 0.8v at the lfb terminal. figure 31 shows the mc34703 linear regulator circuit with its compensation circuit. for example, if r 10 is chosen as 15 k ? (recommended), r 11 will be calculated as 18.75 k ? for the output voltage of 1.8 v; in a same manner, r 11 is 46.87 k ? for the output voltage of 3.3 v. we recommend using 1% tolerance resistors (r 10 and r 11 ) for the precise output voltage. the following table shows the recommended values of and referred to different buck output voltage: v pp ?? i ripple r esr = v reset v out v ldo i out v ldo v ref 1 r 11 r 10 -------- + ?? ?? = table 12. recommendation of and value for different voltage vo r10 (k ? ) r11 (k) ? 0.8 15 ? 1.8 15 18.7 2.0 15 22.6 3.3 15 47 5.0 15 78.7
analog integrated circuit device data 32 freescale semiconductor 34703 typical application logic commands and registers figure 31. linear regulator circuit compensation components setting the compensation component values have been determined by the design. the recommended values are the following: c 25 = 10nf, c 23 =6.8nf, r 7 = 1.5k ? since the compensation component values designed are dependent on the output capacitor value, the capacitance of 10 f for the output capacitor c o is recommended. output current limit setting the current limit of the linear regulator can be adjusted by means of an external current sense resistor r s , see figure 31 . the voltage drop caused by the regulator output current flowing through the curre nt sense resistor is sensed between the ldo and the isns terminals. when the sensed voltage exceeds 45 mv (design), the current limit timer starts to time out while the control circ uit limits the output current. if the over current condition lasts for more than 10 ms, the linear regulator is shut off and tuned on again after 100 ms. this type of operation provides equivalent protection to the analog ?current fold-back? operation. figure 32 shows a sample of the ldo in the over current protection. figure 32. ldo in the over current condition + ldrv lfb + co2 r11 vout c23 c25 r7 r10 lcmp mosfet vin ldo isns rs vref v reset v out v ldo i out
analog integrated circuit device data freescale semiconductor 33 34703 typical application logic commands and registers when the ldo output current (channel 3) reaches and exceeds limit, reset terminal (channel 1) is pulled down immediately. channel 2 is ldo output voltage (3.3 v); channel 4 is buck output voltage (1.8 v). the current limit of the ldo can be set by using the following formula: power mosfet selecting to keep the ldo working under stable operation, low input capacitance is recommended for the external power mosfet. however, if input capac itance is too small, it may lead the feedback loop into an unstable region. in this case, a suggested mosfet for the ldo, is irl2703s or ntd60n02r from on semiconductor. layout guidelines to achieve a working power supply (regulator) design, care must be taken in the pcb layout, not just the electrical design. the pcb layout plays a critical role in the power supply performance. a good pcb layout design will improve regulation parameters and el ectromagnetic compatibility (emc) performance of switching power supply. in order to avoid any inductive or capacitive coupling of the switching power supply noise into the sensitive analog control circuits, the noisy power ground and clean quiet signal ground should be well separated on the pcb board, and connected only at one point. the power routing should be made by heavy traces or area of copper. the power path and its return should be placed, if possible, on top of each other on different layers or opposite side s of the pcb board. the switching power supply input and output capacitors should be physically placed very close to the power terminals (vin2, sw, and pgnd) of the 34703. their ground terminals, together with the 34703 powe r ground terminals (pgnd), should be connected by a single island of the power ground copper to create the ?single island? grounding. the bootstrap capacitor should be tightly connected to the integrated circuit as well. the same guidelines as those for the layout of the main switching buck regulator should be applied to the layout of the low power auxiliary boost regulator and to some extent, the power path of the linear regulator. a four layer pcb is recommended for this product. it is imperative to provide a v out (-) terminal at the ground side of the output capacitors, in order to ensure adequate load regulation. the same is also true for ldo. it is also recommended that the vias on the pcb used to connect the second row of contacts (terminals 13 to 21) on the ic, have a hole diameter no larger than 0.009". r s 45mv i limit ---------------- =
analog integrated circuit device data 34 freescale semiconductor 34703 typical application circuit pcb layouts and bom typical application circuit pcb layouts and bom figure 33. a typical application circuit schematic
analog integrated circuit device data freescale semiconductor 35 34703 typical application circuit pcb layouts and bom table 13. bill of material of a typical application circuit application bill of material note: all bom components are rohs compliant. 4-layer pcb to be smonig (soldermask over nickel gold flash) with micro vias plate d with cu until filled nearly solid (9mil thru-holes plated until diameter < 5mil). part-id value device package & description u1 mc34703 mc34703 pqfn33 freescale power management ic q1 ntltd7900n mosfet chipfet protected power mosfet (on semi) d1 mmsd4148t1g diode sod123 switching diode (on semi) vo, vl red or yel chipled 0603 c9 330 f alel uhn1c331mpd nichicon ultra low impedance c7, c17 10 f alel ecea1eks100 (panasonic ks series) c11, 12, 15 2.2 f ceramic c1206 capacitor c1 100 nf ceramic c1206 capacitor c28 10 f ceramic c1206 ecj-3yb1e106m (panasonic x5r series, digikey# pcc2326tr-nd c14 1 f ceramic c1206 capacitor c29 100 nf ceramic c1206 capacitor c21, c24 33 nf ceramic c1206 capacitor c25, c30 10 nf ceramic c0603 capacitor c23 6.8 nf ceramic c0603 capacitor c19 4.7 nf ceramic c0805 capacitor c26 4.7 nf ceramic c1206 capacitor c22 680 pf ceramic c0603 capacitor c20 100 pf ceramic c0603 capacitor l2 10 h inductor 16t#30awg wound on t26-18 micrometals.com core l2-alt. 10 h inductor 22t#30awg wound on t20=70 micrometals.com core l3 3.2 h inductor 6t#18awg wound on t50- 70d micrometals.com core l3-alt. 2.2 h inductor 9t#18awg wound on t50-18b micrometals.com core rsense .025 noninductive ww resistor wlar025fe (ohmite.com) r1 10k r-us_r0603 r0603 resistor r2 47k r-us_r0603 r0603 resistor r3 33 r-us_r0603 r0603 resistor r4 33 r-us_m1206 m1206 resistor r5 4.7k r-us_r0603 r0603 resistor r7 1.5k r-us_r0603 r0603 resistor r8, r9 5.1k r-us_r0603 r0603 resistor r10 22k r-us_r0603 r0603 resistor r11 47k r-us_r0603 r0603 resistor r12 75 r-us_r0603 r0603 resistor r13 50 r-us_r0603 r0603 resistor r14 10k r-us_r0603 r0603 resistor r17, r18 470 r-us_r0603 r0603 resistor r15, r16 50k 10turn trimpot 3223-w-1-503-e bourns smd trimming potentiometer notes 29. freescale does not assume liabi lity, endorse, or warrant components from external manufacturers that are referenced in circu it drawings or tables. while freescale offers component recommendations in this configuration, it is the customer?s responsibility to valid ate their application.
analog integrated circuit device data 36 freescale semiconductor 34703 typical application circuit pcb layouts and bom figure 34. pcb layer 1 figure 35. pcb layer 2 figure 36. pcb layer 3 figure 37. pcb layer 4
analog integrated circuit device data freescale semiconductor 37 34703 typical application circuit typical waveform characteristics of the evb board typical waveform characteristics of the evb board figure 38. power up sequences (standard mode, v in = 5 v, v output = 1.8 v, v ldo = 3.3 v) figure 39. power down sequences (standard mode, v in = 5 v, v output = 1.8 v, v ldo = 3.3 v) figure 40. power up sequences (inverted mode, v in = 7 v, v output = 5 v, v ldo = 3.3 v) figure 41. power down sequences (inverted mode, v in = 7 v, v outpu t = 5 v, v ldo = 3.3 v) figure 42. output ripple voltage (v in = 5 v, i o = 10 a) figure 43. the same output waveform as figure 40 v out v ldo v out v ldo v out v ldo v out v ldo v ripple v ripple
analog integrated circuit device data 38 freescale semiconductor 34703 typical application circuit typical waveform characteristics of the evb board figure 44. output ripple voltage (v in = 10 v, i o = 10 a) figure 45. the same output waveform as figure 42 figure 46. load transient response (step-up i o = 0.1 a - 5 a) figure 47. load transient response (step-down i o = 5 a - 0.1 a) v ripple v ripple v out i o v out i o
analog integrated circuit device data freescale semiconductor 39 34703 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. pnb suffix 33-terminal pqfn plastic package 98asa10705d issue 0
analog integrated circuit device data 40 freescale semiconductor 34703 packaging package dimensions pnb suffix 33-terminal pqfn plastic package 98asa10705d issue 0
analog integrated circuit device data freescale semiconductor 41 34703 packaging package dimensions pnb suffix 33-terminal pqfn plastic package 98asa10705d issue 0
analog integrated circuit device data 42 freescale semiconductor 34703 packaging package dimensions pnb suffix 33-terminal pqfn plastic package 98asa10705d issue 0
analog integrated circuit device data freescale semiconductor 43 34703 packaging pnb suffix 33-terminal pqfn plastic package 98asa10705d issue 0
analog integrated circuit device data 44 freescale semiconductor 34703 packaging pnb suffix 33-terminal pqfn plastic package 98asa10705d issue 0
analog integrated circuit device data freescale semiconductor 45 34703 revision history revision history revision date description of changes 0.0 initial release 2.0 8/2005 ? implemented revision history page ? incorporated engineering comments ? converted to freescale format 3.0 11/2005 ? added new 98asa10705d drawing ? updated iso drawing 4.0 2/2006 ? updated introduction / features ? revised figure 1, simpli fied application diagram ? revised table 1, terminal definitions ? revised typical application section ? changed table 3, static buck converter peak curr ent limit (high level) max rating from 18 to 19 and ldo internal pull-down mosfet r ds(on), i d = 1.0 a, t a = 25c, v bst = 8.0 v max rating from 3.0 to 3.2 ? condensed bill of material. ? corrected terminal definitions on vbst, reset , clksyn, and gnd (terminal 26) ? corrected images for internal block diagram, te rminal connections, and typical applications to reflect changes made to reset and gnd terminals. ? clarified description of the buck converter in the functional internal block description. ? changed output current slew rate from tbd to 2.5 a/ s.
mc34703 rev 4.0 02/2006 rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp . information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should a buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, the buyer shall i ndemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. i 2 c is a trademark of koninklijke philips electronics n.v. ? freescale semiconductor, inc., 2006. all rights reserved. how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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